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M68Z128 5v, 1 mbit (128kb x8) low power sram with output enable preliminary data ai00647 17 a0-a16 w dq0-dq7 v cc M68Z128 g e2 v ss 8 e1 figure 1. logic diagram a0-a16 address inputs dq0-dq7 data inputs / outputs e1 chip enable 1 e2 chip enable 2 g output enable w write enable v cc supply voltage v ss ground table 1. signal names tsop32 (n) (8 x 20mm) november 1998 1/12 this is preliminary information on a new product now in development or undergoing evaluation. detail s are subject to change without notice. ultra low data retention current 10na (typical) 1.0 m a (max) operation voltage: 5v 10% 128kb x 8 very fast sram with output enable equal cycle and access times: 55ns low v cc data retention: 2v tri-state common i/o low active and standby power automatic power-down when deselected description the M68Z128 is a 1 mbit (1,048,576 bit) cmos sram, organized as 131,072 words by 8 bits. the device features fully static operation requiring no external clocks or timing strobes, with equal ad- dress access and cycle times. it requires a single 5v 10% supply, and all inputs and outputs are ttl compatible. this device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. the M68Z128 is available in tsop32 (8 x 20mm) package.
symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature 65 to 150 c v io (2) input or output voltages 0.3 to v cc + 0.3 v v cc supply voltage 0.3 to 7.0 v i o (3) output current 20 ma p d power dissipation 1 w notes: 1. except for the rating ooperating temperature rangeo stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not i mplied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. 2. up to a maximum operating v cc of 5.5v only. 3. one output at a time, not to exceed 1 second duration. table 2. absolute maximum ratings (1) read mode the M68Z128 is in the read mode whenever write enable (w) is high with output enable (g) low, and both chip enables (e1 and e2) are asserted. this provides access to data from eight of the 1,048,576 locations in the static memory array, specified by the 17 address inputs. valid data will be available at the eight output pins within t avqv after the last stable address, providingg is low, e1 is low and e2 is high. if chip enable or output enable access times are not met, data access will be measured from the limiting parameter (t e1lqv , t e2hqv ,ort glqv ) rather than the address. data out may be indeterminate at t e1lqx ,t e2hqx and t glqx , but data lines will always be valid at t avqv . write mode the M68Z128 is in the write mode whenever the w and e1 pins are low, with e2 high. either the chip enable inputs (e1 and e2) or the write enable input (w) must be de-asserted during address transitions for subsequent write cycles. write be- gins with the concurrence of both chip enables being active with w low. therefore, address setup time is referenced to write enable and both chip enables as t avwl ,t ave1l and t ave2h respectively, and is determined by the latter occurring edge. the write cycle can be terminated by the earlier rising edge of e1, w, or the falling edge of e2. a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 e2 a11 g e1 dq5 dq1 dq2 dq3 dq4 dq6 a15 w a16 a12 nc v cc a14 ai00657 M68Z128 8 1 9 16 17 24 25 32 v ss figure 2. tsop pin connections 2/12 M68Z128
if the output is enabled (e1 = low, e2 = high and g = low), then w will return the outputs to high impedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t dvwh before the rising edge of writeenable, or for t dve1h before the rising edge of e1 or for t dve2l before the falling edge of e2, whichever occurs first, and remain valid for t whdx, t e1hdx or t e2ldx . operational mode the M68Z128 has a chip enable power down feature which invokes an automatic standby mode whenever either chip enable is de-asserted (e1 = high or e2 = low). an output enable (g) signal ai00658b 5.0v out c l = 50pf or 5pf c l includes jig capacitance 1800 w device under test 990 w figure 4. ac testing load circuit input rise and fall times 5ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v note that output hi-z is defined as the point where data is no longer driven. table 4. ac measurement conditions mode e1 e2 w g dq0-dq7 power read v il v ih v ih v ih hi-z active read v il v ih v ih v il data output active write v il v ih v il x data input active deselect v ih x x x hi-z standby deselect x v il x x hi-z standby note :x =v ih or v il table 3. operating modes providesa high speed tri-state control, allowing fast read/write cycles to be achieved with the common i/o data bus. operational modes are determined by device control inputs w, e1, and e2 as summa- rized in the operating modes table. symbol parameter test condition min max unit c in input capacitance on all pins (except dq) v in =0v 9 pf c out (2) output capacitance v out =0v 9 pf notes: 1. sampled only, not 100% tested 2. outputs deselected table 5. capacitance (1) (t a =25 c, f = 1 mhz ) 3/12 M68Z128
symbol parameter test condition min typ max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 1 m a i cc1 (1) supply current v cc = 5.5v, (-55) 30 70 ma i cc2 (2) supply current (standby) ttl v cc = 5.5v, e1 = v ih or e2 = v il ,f=0 0.1 2 ma i cc3 (3) supply current (standby) cmos v cc = 5.5v, e1 v cc 0.3v or e2 0.3v, f = 0 0.4 20 m a v il input low voltage 0.3 0.8 v v ih input high voltage 2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage i oh = 1ma 2.4 v notes: 1. average ac current, outputs open, cycling at t avav minimum 2. all other inputs at v il 0.8v or v ih 2.2v 3. all other inputs at v il 0.3v or v ih v cc 0.3v table 6. dc characteristics (t a = 0 to 70 c; v cc =5v 10%) ai00665 row decoder a a (9) chip enable. input data ctrl dq dq (8) column decoder i/o circuits (8) aa chip enable. e1 w g chip enable memory array v cc v ss e2 figure 3. block diagram 4/12 M68Z128
symbol parameter M68Z128 unit -55 min max t avav read cycle time 55 ns t avqv (1) address valid to output valid 55 ns t e1lqv (1) chip enable 1 low to output valid 55 ns t e2hqv (1) chip enable 2 high to output valid 55 ns t glqv (1) output enable low to output valid 20 ns t e1lqx (3) chip enable 1 low to output transition 5 ns t e2hqx (3) chip enable 2 high to output transition 5 ns t glqx (3) output enable low to output transition 0 ns t e1hqz (2,3) chip enable 1 high to output hi-z 20 ns t e2lqz (2,3) chip enable 2 low to output hi-z 20 ns t ghqz (2,3) output enable high to output hi-z 20 ns t axqx (1) address transition to output transition 5 ns t pu chip enable 1 low or chip enable 2 high to power up 0 ns t pd chip enable 1 high or chip enable 2 low to power down 55 ns notes: 1. c l = 100pf (see figure 4) 2. c l = 5pf (see figure 4) 3. at any given temperature and voltage condition, t eihqz +t ezhqz is less than t eilqx and t ezlqx ,t ghqz is less than t glqx for any given device. table 7. read and standby modes ac characteristics (t a = 0 to 70 c; v cc =5v 10%) ai01078 tavav tavqv taxqx a0-a16 dq0-dq7 valid data valid figure 5. address controlled, read mode ac waveforms note: e1 = low, e2 = high, g = low, w = high 5/12 M68Z128
ai00805 tavav tavqv taxqx te1lqv te1lqx te1hqz tglqv tglqx tghqz valid a0-a16 e1 g dq0-dq7 te2hqv te2hqx valid te2lqz e2 figure 6. chip enable or output enable controlled, read mode ac waveforms ai00806b tpd e2 i cc1 tpu i cc2 50% e1 figure 7. standby mode ac waveforms note: write enable (w) = high 6/12 M68Z128
symbol parameter M68Z128 unit -55 min max t avav write cycle time 55 ns t avwl address valid to write enable low 0 ns t avwh address valid to write enable high 45 ns t ave1h address valid to chip enable 1 high 45 ns t ave2l address valid to chip enable 2 low 45 ns t wlwh write enable pulse width 45 ns t whax write enable high to address transition 0 ns t whdx write enable high to input transition 0 ns t whqx (2) write enable high to output transition 5 ns t wlqz (1,2) write enable low to output hi-z 20 ns t ave1l address valid to chip enable 1 low 0 ns t ave2h address valid to chip enable 2 high 0 ns t e1le1h chip enable 1 low to chip enable 1 high 45 ns t e2he2l chip enable 2 high to chip enable 2 low 45 ns t e1hax chip enable 1 high to address transition 0 ns t e2lax chip enable 2 low to address transition 0 ns t dvwh input valid to write enable high 25 ns t dve1h input valid to chip enable 1 high 25 ns t dve2l input valid to chip enable 2 low 25 ns note: 1. c l = 5pf (see figure 4) 2. at any given temperature and voltage condition, t whqx is less than t wlqz for any given device. table 8. write mode ac characteristics (t a = 0 to 70 c; v cc =5v 10%) 7/12 M68Z128
ai00808 tavav te1hax tdve1h tdve2l a0-a16 e1 w dq0-dq7 valid e2 tave1h tave1l tavwl tave2l te1le1h te2lax tave2h te2he2l te1hdx te2ldx data input figure 9. chip enable controlled, write ac waveforms (1,2) ai00807 tavav twhax tdvwh data input a0-a16 e1 w dq0-dq7 valid e2 tavwh tave1l tave2h twlwh tavwl twlqz twhdx twhqx figure 8. write enable controlled, write ac waveforms notes: 1. output enable (g) = high 2. if e1 goes high or e2 goes low simultaneously with w high, the output remains in a high-impedance state. note: output enable (g) = low 8/12 M68Z128
symbol parameter test condition min typ max unit i ccdr supply current (data retention) v cc =3v,e1 v cc 0.3v or e2 0.3v, f = 0 0.01 1 m a v dr supply voltage (data retention) e1 v cc 0.3v or e2 0.3v, f = 0 2 v t cdr chip disable to power down e1 v cc 0.3v or e2 0.3v, f = 0 0 ns t er (1) operation recovery time t avav ns note: 1. see figure 10 for measurement points. guaranteed but not tested. t avav is read cycle time. table 9. low v cc data retention characteristics (t a = 0 to 70 c) ai00659 data retention mode ter 5v tcdr v cc 3v v dr > 2.0v e1 2.2v e1 v dr 0.3v e2 0.3v e2 0.8v figure 10. low v cc data retention ac waveforms 9/12 M68Z128
speed -55 55 ns package n tsop32 (8 x 20mm) temperature range 1 0 to 70 c example: M68Z128 -55 n 1 ordering information scheme for a listof availableoptions (speed, package,etc... ) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. 10/12 M68Z128
tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.007 a2 0.95 1.05 0.037 0.041 b 0.17 0.23 0.006 0.010 c 0.10 0.20 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 7.80 8.20 0.307 0.323 e 0.50 - - 0.020 - - l 0.40 0.60 0.016 0.024 a 0 5 0 5 n32 32 cp 0.10 0.004 drawing is not to scale tsop32 - 32 lead plastic thin small outline (8 x 20mm) 11/12 M68Z128
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. spec ifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com 12/12 M68Z128

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